Title:
DUPLEX CONTROLLER
Document Type and Number:
Japanese Patent JP3446877
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a duplex controller for surely establishing an operation right to either side within a fixed period without oscillating a flip-flop even when a 1 side and a 2 side respectively request duplex changeover at an optional timing.
SOLUTION: In this duplex controller provided with a 1-side NAND gate 1 for inputting 1-side duplex control signals (dpx ctl1) and 2-side operation right signals (service 2) and outputting 1-side operation right signals (service 1) to a 1-side control equipment, a 2-side NAND gate 2 for inputting 2-side duplex control signals (dpx ctl2) and the 1-side operation right signals and outputting the 2-side operation right signals to a 2-side control equipment and a delay circuit 3 for delaying the 1-side operation right signals and inputting them to the 2-side NAND gate or delaying the 2-side operation right signals and inputting them to the 1-side NAND gate, in the case that the assertion signals of the 1-side and 2-side duplex control signals compete, the side of duplex control signals delayed in the delay circuit is turned to a standby side and which side of the control equipment is to be an operation side or the standby side is established within the fixed period.
Inventors:
Yukio Maniwa
Application Number:
JP34478897A
Publication Date:
September 16, 2003
Filing Date:
December 15, 1997
Export Citation:
Assignee:
Yokogawa Electric Corporation
International Classes:
G06F11/20; G05B9/03; (IPC1-7): G06F11/20; G05B9/03
Domestic Patent References:
| JP236429A | ||||
| JP779140A | ||||
| JP981407A | ||||
| JP5189005A |