To reduce parasitic capacitance between two adjacent word lines by shifting the layout of one of divided cell arrays from other cell arrays by a specified pitch in the bit line direction.

Cell arrays 10a, 10b are divided vertically into two in the direction of word line and one half cell array 10b is shifted by 1/4 pitch in the direction of bit line BL. More specifically the cell array 10a, 10b comprise a plurality of one transistor one capacitor type dynamic memory cells each comprising a charge transfer MOS transistor and a charge storage capacitor arranged in matrix with two cells having a common drain of a cell transistor as a unit. Layout of adjacent cell arrays is shifted by 1/2 pitch from that of two cells in the array direction by arranging the trenches finely.