To increase sensitivity of a sense amplifier by reducing the capacitance between two adjacent bit lines which are adjacent in a DRAM having a half- pitch cell array.

A dynamic semiconductor memory(DRAM) of this device has a half-pitch cell array 10. Arrangement of cells is shifted substantially 1/2 of the pitch of two cells where two rows are made 9 unit, and a drain in the row direction is used in common. Sense amplifiers 14a, which are arranged on one end side of the row direction of the cell array 10 and are connected, corresponding to every other, to a pair of bit lines (BL, /BL) out of bit lines are arranged. Sense amplifiers 14b which are arranged on the other end side in the row direction of the cell array 10 and connected, corresponding to the remaining every other a pair of bit lines, are arranged.