To increase operation speed, prevent enlargement of chip size and ensure facilitation of pattern layout by increasing the capacity of a nonvolatile semiconductor storage device and reducing the capacitive load of bit lines.
A first and a second divided bit lines BLa0 and BLb0 respectively are arranged with respect to one main bit line BL0, and a memory cell array 11 is divided into a plurality of blocks. Selection transistors Q0, Q1, Q4, Q5 and discharge transistors Q2, Q3, Q6, Q7 are arranged on both facing sides of the memory cell array 11. Furthermore, a wiring 20 of a specified potential ARGND and wirings 21, 22 of selection signals DCBLa, DCBLb are arranged. The split bit lines BLa0 and BLb0 of the one main bit line BL0 and split bit lines BLa1 and BLb1 of an adjacent main bit line BL1 are arranged alternately (BLa0, BLb1, BLb0, BLb1 and so on).
YONEYAMA AKIRA
SHIBUSAWA KUNIHIKO
Next Patent: DYNAMIC SEMICONDUCTOR STORAGE DEVICE