Title:
ELECTRONIC PARTS AND THEIR JUNCTION STRUCTURE
Document Type and Number:
Japanese Patent JP3752829
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent the occurrence of a junction defect regardless of having somewhat deviation of parallelism of the bottom of a bonding tool at the time of joining a semiconductor chip to a liquid crystal display panel through an anisotropic conductive adhesive between them.
SOLUTION: Dummy terminals 32 are provided at four corners of the lower face of a rectangular semiconductor chip 4, and dummy terminals 31 are provided on the upper face of a lower substrate 2 of a liquid crystal panel correspondingly to dummy terminals 32. In this case, the height of dummy terminals 31 on the lower substrate 2 is higher than that of connection terminals 12 of the lower substrate 2 by a prescribed extent. Therefore, dummy terminals 31 and 32 at four corners facing each other are brought into contact with each other to act as a stopper in the direction where a pressure is applied when the semiconductor chip 4 is joined on the lower substrate 2 with an anisotropic conductive adhesive 6 between them. As the result, gaps between plural connection terminals 12 and 17 facing each other are equal to a prescribed gap.
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Inventors:
Shinichi Kato
Application Number:
JP10192698A
Publication Date:
March 08, 2006
Filing Date:
March 31, 1998
Export Citation:
Assignee:
CASIO COMPUTER CO.,LTD.
International Classes:
G02F1/1345; H01L21/60; (IPC1-7): G02F1/1345; H01L21/60
Domestic Patent References:
| JP10256426A | ||||
| JP3012948U | ||||
| JP9045807A |
Attorney, Agent or Firm:
Hanawa Yoshio