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Patent Searching and Data


Title:
ELEMENT GROUP FOR EVALUATION AND MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE AND METHOD FOR EVALUATING THE SAME
Document Type and Number:
Japanese Patent JP2003069027
Kind Code:
A
Abstract:

To provide a TEG capable of feeding evaluation contents back at an early stage, and to provide an evaluating method using the TEG.

A TFT in the TEG is manufactured on a substrate different from that for a TFT on a real panel by using steps, liable to generate variation of characteristics, and selected from the manufacturing steps for the TFT on the real panel and the minimally required steps for manufacturing a TFT. The TFT in the TEG can be completed sooner than that on the real panel because the number of steps in the TEG is fewer than that on the real panel, and the evaluation test results of TFT characteristics can sooner be fed back to the manufacturing steps for the real panel. Therefore, the time and the cost required by the manufacturing steps for the panel can be suppressed.


Inventors:
NAKAMURA OSAMU
AKIBA MAI
Application Number:
JP2001254685A
Publication Date:
March 07, 2003
Filing Date:
August 24, 2001
Export Citation:
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Assignee:
SEMICONDUCTOR ENERGY LAB
International Classes:
H01L21/66; H01L23/544; H01L29/786; G01R31/28; (IPC1-7): H01L29/786; G01R31/28; H01L21/66
Domestic Patent References:
JPS61220454A1986-09-30
JPH0410660A1992-01-14
JPS6092653A1985-05-24