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Title:
EMITTER SIGNAL SYSTEM
Document Type and Number:
Japanese Patent JPS5489432
Kind Code:
A
Abstract:

PURPOSE: To realize an emitter signal system strong against noise by providing a latch circuit and a counter which generate home emitter signals and a differentiating circuit and a counter which generate machine emitter signals.

CONSTITUTION: When mechanical clock MCL1 (MC) is inputted to latch circuit LCH, counter CTR2 is triggerred to start counting with mechanical clock MCL2 (SC) when home emitter HEMT is level 1. When CTR2 counts fourteen SCs, HEMT issues a level-0 signal. Circuit LCH is reset by this signal, and noise is prevented from having influences on HEMT signal because noise does not pass through circuit LCH even if noise enters signal MC. When signal MC enters between the fifteenth signal SC and the sixteenth signal MC, an error is detected in emitter check. Machine emitter signal MEMT is generated in counter CTR1 by signal SC; and after the completion of signal HEMT period, emitter control signal EMTCT is generated by differentiating circuit DIF to reset CTR1.


Inventors:
HASHIZUME KIYOUHEI
MATSUKAWA KATSUHIRO
OOTA TOMOMI
Application Number:
JP15831477A
Publication Date:
July 16, 1979
Filing Date:
December 27, 1977
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06K17/00; G06F3/08; G06K13/08; (IPC1-7): G06F3/08; G06K13/08; G06K17/00