PURPOSE: To obtain a cheap MP device by decoding the memory address, which requires to be modified by programmable logic array PLA, and controlling a low- rank MP device by the signal of a high-rank memory patching MP device.

CONSTITUTION: On MP device 106-1, when a ROM address sent onto address bus 102 agrees with the address which is previously programmed, PLA1 sends the patch address corresponding to this ROM address onto data bus 105 through patch memory PM1 and buffer BUF1. Simultaneously, low-priority PLA2 is inhibited from decoding the ROM address to prevent the output of defective ROM 103 from being outputted onto data bus 105. When the ROM address on bus 102 does not agree with the address which is previously programmed by PLA1, data of memory PM1 is inhibited from being outputted onto bus 105, and PLA2 is allowed to decode this data. Then, PLA2 performs the same operation as PLA1 and sends indefective information of ROM to bus 105.