PURPOSE: To make the data transfer processing efficient by accepting the next store signal after completion of the end signal corresponding to the fetch only when store follows fetch in respect to two memory access requests.

CONSTITUTION: When a fetch request from channel unit 8-0 is first issued and a store request from unit 8-1 is next issued, a memory end signal is issued from the main memory side to access request processing circuit 10 corresponding to this first fetch and is transferred onto data buffer 9. Next, data corresponding to the store request is temporarily stored in buffer 9 and is transferred to the main memory. In case of store-store, store-fetch and fetch-fetch except this combination, the priority processing is performed only by judgement of circuit 10, and the second request is accepted without waiting for the processing of the first access in respect to two access requests which occurred in order. As a result, it is possible to process data transfer with a high efficiency.