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Patent Searching and Data


Title:
ERROR DETECTING METHOD, ERROR CORRECTING METHOD AND ERROR CORRECTING DEVICE FOR RECEIVED SIGNAL
Document Type and Number:
Japanese Patent JP2001102938
Kind Code:
A
Abstract:

To improve the reliability of a received signal when digital data are sent and received.

A decoding device 20 receives a transmit signal to which parity check bits are added after an input signal to be sent is processed by cyclic Hamming encoding using a generating polynomial and is equipped with a parity check part 21 which checks whether or not there is a 1-bit error by checking the parity of the receive signal, a cyclic Hamming code check part 23 which checks the receive signal except the parity check bits, a decision part 24 which judges that no error is generated when neither the parity check part 21 nor the cyclic code check part 23 detects an error, decides that a 1-bit error is generated when both the parity check part 21 and cyclic Hamming code check part 23 detect an error, and decides that transmission abnormality occurs when only the cyclic Hamming code check part 23 detects an error, and an error correction and decoding part 25.


Inventors:
KISHIBE SHINICHI
Application Number:
JP27868199A
Publication Date:
April 13, 2001
Filing Date:
September 30, 1999
Export Citation:
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Assignee:
ICOM INC
International Classes:
H03M13/09; H03M13/15; H03M13/19; H03M13/29; H04L1/00; (IPC1-7): H03M13/09; H04L1/00
Attorney, Agent or Firm:
Katsunori Sugimoto (1 outside)