Title:
ERROR DETECTION SYSTEM
Document Type and Number:
Japanese Patent JPH0512050
Kind Code:
A
Abstract:
PURPOSE: To improve the diagnostic performance.
CONSTITUTION: An information processor 1 sends a signal group 10 to an information processor 2. The information processor 2, equipped with LSIs 3 and 4, receives the signal group 10 from the information processor 1. The LSI 3 receives the signal group 10 to perform various operations as well as the parity check for the signal group 10. The LSI 4 also receives the signal group 10 and performs various operations as well as the parity check for the signal group 10.
More Like This:
| JP2021536082 | Data state synchronization |
| JP2003101972 | TMCC DECODING CIRCUIT |
| JPS60144848 | CACHE MEMORY CONTROL SYSTEM |
Inventors:
YAMAUCHI MAKOTO
Application Number:
JP16786791A
Publication Date:
January 22, 1993
Filing Date:
July 09, 1991
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F11/10; G06F11/16; H03M13/00; (IPC1-7): G06F11/10; G06F11/16; H03M13/00
Attorney, Agent or Firm:
Uchihara Shin
Next Patent: 複合加工工作機械