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Title:
EXCLUSIVE OR CIRCUIT
Document Type and Number:
Japanese Patent JPH01236816
Kind Code:
A
Abstract:

PURPOSE: To curtail the number of elements by expanding the logical amplitude of a gate circuit for contrast and setting and deciding the reference voltage of an external gate circuit to contrast these levels and a reference voltage to the vicinity of the center of a high level and an intermediate level.

CONSTITUTION: Resistances RC5 and RC6 for a collector are made 1.2times as much as the resistance value for a conventional collector and a logical amplitude is expanded. A circuit is connected to outputs C and D, a reference voltage VREFE is set to the inverse of 0.93V, and thus, an intermediate level is considered as a low level and operated. Consequently, the EX-OR signal of input signals A and B can be obtained to the collector output of a transistor TR 11. Thus, the EX-OR circuit can be composed of five transistors for an internal gate, five resistances for an internal gate, four transistors for an external gate and three resistances.


Inventors:
YANO HARUO
Application Number:
JP6510188A
Publication Date:
September 21, 1989
Filing Date:
March 17, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K19/21; (IPC1-7): H03K19/21
Attorney, Agent or Firm:
Uchihara Shin



 
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