PURPOSE: To correctly read a counter value with a small software load by prohibiting the register value updating of plural registers while the register value of plural registers is read after the register transfer completion with a processor.

CONSTITUTION: While a processor 5 divides and reads registers 41∼43, register value updating is prohibited. Thus, even when a counter 3 is changed during the dividing and reading, the processor 5 can correctly divide and read the value before the counter value is changed and a conventional erroneous reading is prevented. Since a register value reading starting is executed after the register transfer completion, a stable counter value can be read and a conventional 'double reading' is made unnecessary.