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Title:
EXTERNAL SYNCHRONIZATION CLOCK PULSE GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPH02171049
Kind Code:
A
Abstract:

PURPOSE: To prevent the occurrence of a frequency jump to the clock output of a voltage controlled oscillator due to the switching of a clock pulse selection circuit even when the phases of external input clocks before and after the switching are different from each other by providing a phase adjustment circuit.

CONSTITUTION: A phase adjustment circuit 1 receives plural external clocks whose phases are not coincident to make the phases of all the clocks coincident. Then a clock pulse selection circuit 2 selects one of clocks of the same phase and gives an output to a phase comparator 3. The comparator 3 compares the phase of the selected clock with the phase of the output clock pulse from a voltage controlled oscillator 4 and outputs a DC voltage proportional to the phase difference. Then the oscillator 4 outputs the clock phase of the frequency controlled by the DC voltage and the clock pulse synchronously with an external input clock is obtained. Thus, even if there is a phase difference between external input clocks before and after the switching, the occurrence of a frequency jump at the clock output of the oscillator 4 is prevented by the switching of the selection clock of the circuit 2.


Inventors:
FUJIMAKI SHIGEO
NISHIKAWA KAZUO
Application Number:
JP32738288A
Publication Date:
July 02, 1990
Filing Date:
December 23, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L7/00; H04L7/033; (IPC1-7): H04L7/00
Attorney, Agent or Firm:
Toshi Inoguchi



 
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