PURPOSE: To compensate a delay time for a receiver and a driver and to allow the deviation in transmission/reception timing to be within the standards by providing a phase shift circuit shifting the phase of a lock signal stepwise and a selector.

CONSTITUTION: A signal received by a receiver 1 is fed to a frame decomposing section 6 and a clock extraction section 2, a data is fed to a driver 3 from a frame composing section 7 via a FF 8 and the data is sent based on a clock signal extracted from the clock extraction section 2. In this case, a phase shift circuit 4 consists of a shift register or the like, a clock signal extracted by the clock extraction section 2 by a high speed clock signal is shifted to output plural clock signals having stepwise phase differences in parallel. Then the clock signal of a desired phase of plural clock signals is selected by a selector 5 to obtain a transition clock. Thus, the delay time of the receiver 1 and the driver 3 is compensated to allow the deviation of the transmission/reception timing to be within the standards.