To attain high integration and high performance of a vertical MOS transistor.
A planar semiconductor layer is formed on an insulating film on a substrate and a columnar semiconductor layer is formed on a plurality of planar semiconductor layers, the planar semiconductor layer is separated into elements, and an impurity region is formed on the planar semiconductor layer. Subsequently, an insulating film is formed on at least a part of the surface, a conductive film is formed on the insulating film, the insulating film and the conductive film are etched back, the insulating film and the conductive film on the side of the columnar semiconductor layer are formed with a desired length, a gate electrode is formed, the conductive film and the insulating film are removed selectively by etching, the gate electrode and gate wiring extending therefrom are formed, and a first silicide layer is formed to connect at least a part of the surface of an impurity region formed on the planar semiconductor layer of the first MOS transistor with at least a part of the surface of an impurity region formed on the planar semiconductor layer of the second MOS transistor, out of a plurality of MOS transistors corresponding to the plurality of columnar semiconductor layers, respectively.
ARAI SHINTARO
Fumiaki Otsuka
Takaki Nishijima
Hiroyuki Suda
Nobuyuki Taniguchi