To downsize a vertical MOS transistor while reducing the parasitic resistance and capacitance which increase as the vertical MOS transistor is downsized.
A semiconductor device includes a substrate, an insulating film on the substrate, a planar semiconductor layer formed on the insulating film on the substrate, and first and second MOS transistors each including a first drain/source region formed on the planar semiconductor layer, a columnar semiconductor layer formed on the planar semiconductor layer, a second source/drain region formed above the columnar semiconductor layer, and a gate electrode formed through an insulating film to surround the sidewall of the columnar semiconductor layer, wherein the area of the upper surface of the second source/drain region of the first or second MOS transistor is larger than the area of the upper surface of the columnar semiconductor layer of the first or second MOS transistor, and a silicide layer is formed to connect at least a part of the surface of the first drain/source region of the first MOS transistor with at least a part of the surface of the first drain/source region of the second MOS transistor.
ARAI SHINTARO
Fumiaki Otsuka
Takaki Nishijima
Hiroyuki Suda
Nobuyuki Taniguchi
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