Title:
FAST LEARNING SYSTEM OF MEURAL CIRCUIT NETWORK
Document Type and Number:
Japanese Patent JP3281020
Kind Code:
B2
Abstract:
PURPOSE: To learn data without destroying recognizing ability for the data learned in the past.
CONSTITUTION: A neural circuit network 21 processes data in real time. When the data which the neural circuit network 21 can not discriminate occurs, a learning unit, by using a learning neural circuit network 22 which is a copy of the neural circuit network 21, calculates the range within which the structure of neural circuit network 21 can be changed within the range the neural circuit network can output correctly far the data already learned, and then, calculates correction amount of the structure of the neural circuit network 21 which is required far the neural circuit network 21 to learn a new data, so as to decide whether the correction amount is within the permitted range of correction. If the correction amount is within a possible range of correction, the learning unit corrects the structure of learning neural circuit network 22 and then copies it to the neural circuit network 21. If the calculated correction amount is not within a possible range of variation, the learning unit make a learning neural circuit network 23 learn the data of both already learned and not yet learned, and after the learning, copies them to the neural circuit network 21.
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Inventors:
Toshiaki Hatano
Application Number:
JP4148592A
Publication Date:
May 13, 2002
Filing Date:
February 27, 1992
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F15/18; G06G7/60; G06N3/08; G06N99/00; (IPC1-7): G06N3/08; G06G7/60
Domestic Patent References:
| JP4372044A | ||||
| JP512465A |
Other References:
【文献】益岡竜介、他4名,バックプロパゲーションにおける高速アルゴリズムの研究 -追記学習-,情報処理学会第38回(昭和64年前期)全国大会,日本,情報処理学会,6F-5,P.492
Attorney, Agent or Firm:
Takehiko Suzue