Title:
FLASH MEMORY
Document Type and Number:
Japanese Patent JP3787167
Kind Code:
B2
Abstract:
PURPOSE: To provide a chip mechanism extremely displaying flexibility in the case of being used in an application and controlling a flash memory increasing the entirely throughput of executing operation.
CONSTITUTION: The flash memory 310 is provided with a user interface 40 and a flash array controller 50. The user interface 40 is provided with a function receiving a user demand issued from a processor and holding together plural demands to be executed. Further, the user interface is also provided with the function controlling the priority of the demand to be executed. The operation on the flash array such as programming and erasing or the like is executed with the array controller 50. A array controller 40 is a general processor having a program memory programmable by the user. One or plural algorithms capable of executing with the array controller are stored in the program memory. The algorithm is selected in accordance with the demand received with the user interface 40. Since each array is allowed to operate in parallel, the operation input is increased.
Inventors:
Micky Lee Flandrich
Richard Joseph Durant
Keith Fredrick Underwood
Rodney Earl Rosman
Richard Joseph Durant
Keith Fredrick Underwood
Rodney Earl Rosman
Application Number:
JP16585994A
Publication Date:
June 21, 2006
Filing Date:
June 27, 1994
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G11C16/02; G11C17/00; G06F9/445; G06F9/48; G06F12/00; G11C16/10; (IPC1-7): G11C16/06; G06F12/00
Domestic Patent References:
| JP2257496A | ||||
| JP3010323A | ||||
| JP61054540A |
Attorney, Agent or Firm:
Masaki Yamakawa
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