Title:
FLOATING GATE MEMORY ARRAY
Document Type and Number:
Japanese Patent JPH02275668
Kind Code:
A
Abstract:
PURPOSE: To reduce the electrostatic capacity of bit lines itself and drain floating gate and also reduce the size of a memory cell, and make that effective to an erasable and programmable ROM(EPROM) array by forming silicide- processed areas on respective streaks of conductors. CONSTITUTION: Silicide-processed bit lines 2 and 4 have relatively low resistance values, a parallel metal conductor equipped with many bit line connection parts is not needed, and an array 1 has relatively small bit line electrostatic capacity and is formed in structure of relatively small size. Word lines 13 and silicide- processed bit lines 2 and 4 are separated by thick field oxide, P/N junction, or trench separation. The word lines 13 are formed of a silicide-processed polycrystalline substance or other materials having a low resistance value. The combination of a program write voltage and an erasure voltage is improved by using an insulator having a relatively high dielectric constant. Consequently, programmable memory cell high-density crossing type array structure is obtained.
Inventors:
MANTSUAA GIRU
DEIBITSUDO JIEE MATSUKERUROI
DEIBITSUDO JIEE MATSUKERUROI
Application Number:
JP29379189A
Publication Date:
November 09, 1990
Filing Date:
November 10, 1989
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Akira Asamura (3 outside)