PURPOSE: To establish frame synchronization of the ATDM system by shifting one bit when the number of counted synchronizing pattern dissident number reaches a set value.

CONSTITUTION: Every time a dissidence detection pulse (c) is outputted from a synchronizing pattern detection circuit 2, an AND circuit 6 outputs a pulse (g) to a counter 7. A comparator 8 compares a preset with a count outputted from a counter 7 and when the count is coincident with the set value, a clock pulse output inhibition pulse (i) to a clock pulse extraction circuit 10. The frame pulse outputted by the frame counter 11 retards the clock pulse by one bit, resulting that the detection position in the synchronizing pattern detection circuit 2 is shifted by one bit. Till the true synchronizing position is detected, the shift of the synchronizing pattern detection position is continued and the synchronization is restored finally.