PURPOSE: To attain the arithmetic of a full adder with no error even though the input data change in a short time by allocating the data on plural augends, addends and carries which are supplied successively to plural full adders and performing arithmetic in parallel to each other.

CONSTITUTION: The augends A, addends B and carries C0 supplied to terminals 1W3 respectively are latched by latch circuits LA11W31 when rotary switches RS1W5 have contacts with terminals RS11W15. These data are supplied to a full adder FA1 with the prescribed timing for execution of an arithmetic A+B+C0. Then an addition result Σ is delivered to an output terminal OΣ of the FA1 and supplied to a terminal 4 via a terminal RS41. While a carry C3 produced by the addition is delivered to an output terminal OC3 and then to a terminal 5 through a terminal RS51. When said data A, B and C0 are latched by the circuits LA11W31 respectively, the rotary switches are changed immediately to the next notch respectively. Thus the arithmetics are carried out by full adders FM1WFA4 in parallel.