To provide a function verification generation unit capable of preparing the function verification description to verify function verification items of a circuit to be verified even when a person in charge of verification does not learn HDL or a verification description language other than HDL, a designer who has learned HDL does not learn the verification description language other than HDL, or the function verification description itself described in HDL is not verified, and a description method in which a designer or a person in charge of verification clearly and uniformly describes the verification content of the circuit operation by using a timing diagram.
The function verification description generation unit having a means to input the logical relationship between wave profiles and the generation information of the logical relationship in the timing diameter and a means to generate the verification description from the timing diagram based on the logical relationship between the wave profiles and the generation information of the logical relationship comprises a terminal information extracting unit 1, a timing diagram editing unit 2, a verified operation extracting unit 3, and a verification description generation unit 4.
ARA HIROMI
SUZUKI TAKASHI
ITO MASAKI
UCHIBE KONAGI
