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Title:
METHOD AND DEVICE FOR EVALUATING NOISE TOLERANCE OF SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM
Document Type and Number:
Japanese Patent JP2003216682
Kind Code:
A
Abstract:

To provide a method and a device for evaluating tolerance of a semiconductor device against external noises.

In a noise tolerance evaluation method, a circuit including the semiconductor device for evaluation is realized by an equivalent circuit 100 in which an object equivalent circuit 104 to realize the semiconductor device, a noise source equivalent circuit 101 which realizes a noise source outside the semiconductor device and inputs the noise to the object equivalent circuit, and an external equivalent circuit 102 to realize a circuit outside the semiconductor device are connected in parallel to each other, and the noise tolerance is evaluated with the voltage and the current generated in the object equivalent circuit by the noise as a cause of malfunction, and the noise tolerance to the external noise of the semiconductor device can be evaluated considering the effect of the circuit outside the semiconductor device.


Inventors:
TAKAHASHI EIJI
SAITO YOSHIYUKI
FUKUMOTO YUKIHIRO
BENNO HIROSHI
Application Number:
JP2002311574A
Publication Date:
July 31, 2003
Filing Date:
October 25, 2002
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Nakajima Shiro