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Title:
HIGH VOLTAGE FINAL OUTPUT STAGE
Document Type and Number:
Japanese Patent JPH11205122
Kind Code:
A
Abstract:

To combine a voltage shift driving circuit having the functional and constitutional features usable by both high voltage and low voltage and capable of reducing the area of a circuit further with a final output stage for supplying power to a load.

In this high voltage final output stage for electric load driving which is constituted of a pair of the transistors of complementary combination connected between a first reference power source (Vdd) and a second reference power source (Vss) and in which the pair of the transistors are constituted by connecting in series at least one PMOS pull-up transistor (MP1) to an NMOS pull-down transistor (MN), an additional PMOS transistor (MP2) is connected in parallel to the PMOS pull-up transistor (MP1) and its body terminal is made to be in common with the PMOS pull-up transistor (MP1).


Inventors:
DEPETRO RICCARDO
MARTIGNONI FABRIZIO
SCIAN ENRICO
Application Number:
JP31113198A
Publication Date:
July 30, 1999
Filing Date:
October 30, 1998
Export Citation:
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Assignee:
ST MICROELECTRONICS SRL
International Classes:
H03K17/10; H03K17/687; H03K19/0175; H03K19/0185; (IPC1-7): H03K19/0175; H03K17/10; H03K17/687
Attorney, Agent or Firm:
Soga Doteru (6 people outside)