Title:
スキャンパス回路およびそれを備える論理回路ならびに集積回路のテスト方法
Document Type and Number:
Japanese Patent JP4265934
Kind Code:
B2
Abstract:
A scan-path circuit is made up of cascaded flip-flops which are input/output circuits of a combinational logic circuit. In a logic circuit 21 which adopts a scan design test technique for simplifying a test of the same by serially shifting a test result through the flip-flops, selectors for directly connecting inputs of the respective flip-flops of the scan-path circuit to a scan input are provided. After causing all flip-flops to have identical values (either "0" or "1"), the values are shifted and outputted so that the location of a failure is specified. With this, the maximum period of time required by the test does not exceed the total of clocks for the shifting through all stages and one more stage. Thus, in addition to the checking of the presence of a failure, the location of a failure is, if necessary, specified in a short period of time.
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Inventors:
Tomoya Takasaki
Application Number:
JP2003162913A
Publication Date:
May 20, 2009
Filing Date:
June 06, 2003
Export Citation:
Assignee:
Sharp Corporation
International Classes:
G01R31/28; G01R31/3185; G06F11/22; H01L21/66; H01L21/822; H01L27/04
Domestic Patent References:
| JP9281194A | ||||
| JP6230075A | ||||
| JP2141682A |
Attorney, Agent or Firm:
Kenzo Hara International Patent Office
Kenzo Hara
Ryuichi Kijima
Ichiro Kaneko
Kenzo Hara
Ryuichi Kijima
Ichiro Kaneko