PURPOSE: To provide a computer structure for executing indirect address and chart retrieval by a computer in a parallel processing structure according to a single instruction type and multiple data type execution model.

CONSTITUTION: This device is provided with a processing element shift register 29 which receives and holds local memory offset address values calculated or loaded by related processing elements according to the first preliminarily decided set of an instruction. This processing element shift register 29 transfers the content to a local memory shift register 29 of a local memory related with the processing elements by bit units. A bit value at the bit position of the highest-order digit is successively transferred to the bit position of the lowest- order digit of the local memory shift register 29 according to the second preliminarily decided set of the instruction.