Title:
IMAGE PROCESSOR
Document Type and Number:
Japanese Patent JP3410119
Kind Code:
B2
Abstract:
PURPOSE: To access a large amount of continuous asynchronous data at high speed.
CONSTITUTION: This processor is provided with a mode switching means 37 which can switch a mode to an asynchronous mode accessing in asynchronizing with an internal clock CK1 and can return to an original internal clock synchronizing operation mode after finishing access by the asynchronous mode by the on/off of a specified terminal at the time of writing/reading to a synchronous type device by external CPU. Thus, the signals of the address bus, the data bus, the chip select and W/R of an internal device are switched to the side of external CPU with a signal Sel synchronizing with an internal clock CK1 and then, the device is made to access by a clock cycle on the side of external CPU. Thus, it takes time to switch the mode because of a clock cycle on the side of the processor, but the device can quickly be accessed with the clock cycle on the side of external CPU at the time of the actual access of the device.
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Inventors:
Hiroyuki Kawamoto
Application Number:
JP13224692A
Publication Date:
May 26, 2003
Filing Date:
May 25, 1992
Export Citation:
Assignee:
株式会社リコー
International Classes:
G06F3/08; G06F12/00; H04N1/21; (IPC1-7): H04N1/21; G06F3/08
Domestic Patent References:
| JP1271247A | ||||
| JP1241457A | ||||
| JP448489A | ||||
| JP23172A | ||||
| JP1129657A | ||||
| JP5525173A |
Attorney, Agent or Firm:
Akira Kashiwagi (1 person outside)