To decrease critical data loss by switching the mode of a cache according to a battery rest detection result.

The rest of a battery is detected by a method for measuring a voltage value, a method for integrating a current value, etc. When the rest of the battery decreases below a predetermined threshold value, a battery rest detection part 208 holds an interruption signal at Low level to inform a CPU 201 of the decrease. Here, the interruption signal is an active low signal. The CPU 201 once receiving the interruption signal calls a switching program stored in a ROM 205 and switches the cache mode from a write-back mode to a write- through mode. Writing to the cache memory 202 is temporarily stopped first and the write data stored currently in the cache memory 202 are all transferred to an actual memory. Then the cache mode is switched to the write-through mode.