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Patent Searching and Data


Title:
DATA SWAP MANAGEMENT SYSTEM FOR MAIN STORAGE DEVICE
Document Type and Number:
Japanese Patent JPH11120080
Kind Code:
A
Abstract:

To prevent a performance decrease due to frequent gathering of an error log by generating a swap address avoiding an area of a main storage device where a 1-bit error has occurred if the 1-bit error is detected.

An error detecting and correcting means 30 when detecting a 1-bit error of data accessed on the main storage device 20 corrects the error and sends an error signal out to an error history holding means 60. A reference address sending-out means 40 sends the accessed address of the main storage device 20 out to an error history holding means 60. The error history holding means 60 receives the error signal and holds a history of 1-bit errors by areas as data swap units of the main storage device 20. A processor 50 functioning as a swap address generating means when generating a swap address showing the area of the main storage device 20 to be swapped refers to this error history and avoid an area where a 1-bit error occurred.


Inventors:
MISHIMA TAKAKAZU
Application Number:
JP29949097A
Publication Date:
April 30, 1999
Filing Date:
October 16, 1997
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F12/12; (IPC1-7): G06F12/12
Attorney, Agent or Firm:
Masao Matsumoto