To provide an information processor for improving performance by shortening the amount of time required for acquiring the in-device data of an interrupt request source to refer to when a processor in a host device performs interrupt processing.

A reference data storage part 33 is provided at a position where access latency is shorter than that of devices 50, 60, 70, and 80 when it is viewed from a CPU 31. The devices 50, 60, 70 and 80 transfer data in the devices 50, 60, 70 and 80 to refer to when the CPU 31 performs interrupt processing in response to interrupt requests from the devices 50, 60, 70 and 80 to a reference data storage part 33 in advance for updating the data, and the CPU 31 performs the interrupt processing by referring to the data in the devices 50, 60, 70 and 80 stored in the reference data storage part 33 when the interrupt requests are made from the devices 50, 60, 70 and 80.