To obtain an information processor having a high flexibility by enhancing the efficiency of parallel accumulation processing.
The initial value of a reading address is set in an initial address register A 109, and the initial value of a writing address is set in an initial address register B 111, and the number of accumulation data to be accumulated by an accumulator 103 and the number of times of repetition are set in a number of times of accumulation register 110. A controller 107 controls the output timing of the initial value of a reading address under a memory controller A 106 and the timing of initialization by an initializer 105 and the output timing of a writing address under a memory controller B 108. A series of processing of data reading, accumulation, and data writing is executed in parallel.
KAMEMARU TOSHIHISA
SUZUKI KOICHI
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