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Title:
INSTRUCTION FETCH CIRCUIT
Document Type and Number:
Japanese Patent JP2006235723
Kind Code:
A
Abstract:

To conduct branch prediction of a branch instruction formed of a plurality of words at a high speed in a processor of a pipeline system.

The branch prediction is conducted at a stage that a part of the branch instruction formed of the plurality of the words is fetched. When branch prediction information is obtained from a branch target buffer (BTB) or the like, an instruction of a predicted branch destination is fetched without fetching a remaining part of the branch instruction. Thereby, the branch instruction formed of the plurality of the words is processed at an execution cycle of one word as long as the branch prediction succeeds. A penalty when the branch prediction is failed is same as in a case that the branch instruction is formed of one word.


Inventors:
TAKAMATSU KOTA
Application Number:
JP2005045661A
Publication Date:
September 07, 2006
Filing Date:
February 22, 2005
Export Citation:
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Assignee:
SONY CORP
International Classes:
G06F9/38
Domestic Patent References:
JPS63124135A1988-05-27
JPS63124135A1988-05-27
Other References:
JPN6009052653, David A.Patterson  John L.Hennessy, コンピュータ・アーキテクチャ−設計・実現・評価の定量的アプローチ−, 19921225, 1版, P.302−P.307, JP, 日経BP社
Attorney, Agent or Firm:
Toshikazu Marushima