Title:
INTEGRATABLE ACTIVE DIODE
Document Type and Number:
Japanese Patent JPH02275674
Kind Code:
A
Abstract:
PURPOSE: To protect an integrated logic part against a reverse voltage by forming a highly-doped deep area which is connected to the source of a MOS transistor(TR) of a 1st conduction type extending from the top surface of a well. CONSTITUTION: The well 64 represents an upper well surface 69 and a lower well surface 70 positioned between the well and a substrate 60, a highly-doped P<+> area 71 has the upper well surface formed and is connected to a source area 66 through a conduction layer 72, and the area 71 can extend to a lower well 70. This structure includes an NPN type bipolar TR, which has its emitter composed of the drain area 67 of a TR TS, its base composed of the well 64, and its collector composed of drain layers 60 and 74 of a vertical power MOS TR. Consequently, the logic part can securely be protected when abrupt polarity inversion is caused.
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Inventors:
ANTOWAN PABURIN
Application Number:
JP23836289A
Publication Date:
November 09, 1990
Filing Date:
September 13, 1989
Export Citation:
Assignee:
SGS THOMSON MICROELECTRONICS
International Classes:
H01L29/78; H01L21/822; H01L21/8234; H01L27/02; H01L27/04; H01L27/088; (IPC1-7): H01L29/784
Attorney, Agent or Firm:
Tadahiko Ito (2 outside)
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