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Patent Searching and Data


Title:
P-CHANNEL TYPE INSULATED GATE BIPOLAR TRANSISTOR
Document Type and Number:
Japanese Patent JPH02275673
Kind Code:
A
Abstract:

PURPOSE: To prevent an avalanche breakdown at the time of turning OFF by specifying the thicknesses, specific resistances and secondary breakdown voltages of second and third layers.

CONSTITUTION: The thickness of a second layer 2 is 15μm or more, and specific resistance of a third layer 3 is 250Ωcm or more. When the thicknesses of the layers 2, 3 are W2, W3μm, the specific resistances of the layers 2, 3 are ρ2, ρ3μm, and a secondary breakdown voltage is VCEXV. When the value of W /ρ2×ln(ρ3×W3)×10-3 is A, it is assumed that the A exists in a range between a line passing points (450, 2.4), (900, 4.0), (1250, 7.1) and a line passing points (450, 19.8), (900, 30.0), (1250, 36.6) for predetermined VCEX with VCEX at an x axis and the A at a y axis in orthogonal coordinates. Thus, avalanche carrier is scarcely generated at the time of turning OFF.


Inventors:
IWAMURO NORIYUKI
Application Number:
JP32877089A
Publication Date:
November 09, 1990
Filing Date:
December 19, 1989
Export Citation:
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Assignee:
FUJI ELECTRIC CO LTD
International Classes:
H01L29/68; H01L29/739; H01L29/78; (IPC1-7): H01L29/68; H01L29/784
Attorney, Agent or Firm:
Iwao Yamaguchi