Title:
集積回路設計システム、方法及びプログラム
Document Type and Number:
Japanese Patent JP4365274
Kind Code:
B2
Abstract:
When a simulation model generation unit converts logic on the gate level into a basic primitive which can be executed by a simulator to generate a simulation model, for the basic primitives a degeneracy processing unit determines and deletes a gate which can be deleted and which will not affect the delay stage count. The degeneracy processing unit is provided with a constant gate degeneracy unit which puts a plurality of constant gates together, a buffer degeneracy unit which deletes fan-out-free buffers and an identical fan-in gate degeneracy unit which puts identical fan-in gates together.
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Inventors:
Go Mochizuki
Application Number:
JP2004180941A
Publication Date:
November 18, 2009
Filing Date:
June 18, 2004
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06G7/62; G06F17/50; H01L21/82
Domestic Patent References:
| JP2001022808A | ||||
| JP63223926A |
Attorney, Agent or Firm:
Susumu Takeuchi