INTEGRATED CIRCUIT AND FORMING METHOD THEREOF

Title:

INTEGRATED CIRCUIT AND FORMING METHOD THEREOF

Document Type and Number:

Japanese Patent JPH0786523

Kind Code:

A

Abstract:

PURPOSE: To provide an integrated circuit containing inductive and capacitive elements while having a contracted semiconductor die area and a forming method thereof. CONSTITUTION: The integrated circuit is formed of a first conductive material layer 30 separated from a second conductive material layer 39 by a dielectric material layer 36. The first conductive material layer 30 is patterned, and first plates 32 for a capacitor are formed. Electric interconnecting sections 33 are formed into the first plates 32 respectively. A passage 37 is shaped into the dielectric material layer 36. The second conductive material layer 39 is patterned, and second plates 42 for the capacitor and plate spiral inductors 21 are formed. The plate spiral inductors 21 are surrounded by the second plates 42 for the capacitor.

Inventors:

JIYOSEFU SUTAUDEINGAA
WAREN ERU SHIIRII
HAUWAADO DABURIYU PATAASON

Application Number:

JP22900794A

Publication Date:

March 31, 1995

Filing Date:

August 31, 1994

Export Citation:

Click for automatic bibliography generation Help

Assignee:

MOTOROLA INC

International Classes:

H01G4/40; H01L21/822; H01L27/04; H01L27/08; H03H5/02; H03H7/075; (IPC1-7): H01L27/04; H01G4/40; H01L21/822

Attorney, Agent or Firm:

Masanori Honjo (1 person outside)

Next Patent: OXIDE FILM FORMING METHOD