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Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5994864
Kind Code:
A
Abstract:

PURPOSE: To make planar type and effectively prevent a leak current flowing toward a substrate, electrical interference between elements, etc. by a method wherein an element having a solid layer structure is buried in an insulation layer, and then a semiconductor element having a planar structure is formed on the insulation layer.

CONSTITUTION: A stripe type laser having a double hetero structure is formed on a substrate composed of semi-insulation gallium arsenide. An insulation layer 7 is formed, and a layer 8, made of n type gallium arsenide, which serves as FET operating layer is formed. The layer 8 is removed by patterning, and a negative electrode wiring 11 of the laser is formed by forming an aperture 10 for forming a positive electrode 9 of the laser. A source electrode 12, a drain electrode 13, and a gate electrode 14 are formed on an FET operating layer 8', and the drain electrode 13 is connected to the laser negative electrode 11. A wiring electrode 15 is formed. The structure of an integrated circuit consisting of the FET and the stripe type laser becomes almost planar type, which is effectively contributed to increase the integration.


Inventors:
YAMAGOSHI SHIGENOBU
Application Number:
JP20481282A
Publication Date:
May 31, 1984
Filing Date:
November 22, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L27/00; H01L27/14; H01L27/15; H01S5/026; (IPC1-7): H01L27/02; H01L27/14
Attorney, Agent or Firm:
Koshiro Matsuoka



 
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