Title:
INTEGRATED LOGIC CIRCUIT HAVING SINGLE END INPUT LOGIC GATE
Document Type and Number:
Japanese Patent JP3530582
Kind Code:
B2
Abstract:
PURPOSE: To provide a logic circuit which fast operates with low voltage by changing the voltage level of a control electrode means in the direction that is opposite to the change of a logic input terminal voltage level which occurs in a pair of differential input terminals.
CONSTITUTION: When the input terminal A of a transistor Tr Q1 becomes an H level and the input terminal B of a Tr Q2 becomes an L level, current flows through Trs Q5 and Q6 of each pair of differential Trs Q4 and Q5, and Q6 and Q7. Because the current that flows through the Tr Q5 also flows through resistance R3 which reduces base voltage of the Q3, when the base voltage of the Tr Q1 is high and the base voltages of the Trs Q2 and Q3 are low, the Tr Q1 is conductive, an output terminal O becomes an H level and an inversion O becomes an L level. When both input terminals A and B are on an L level, current flows through the Trs Q4 and Q6 and the base voltage of the Tr Q3 becomes an H level. Then, the Trs Q1 and Q2 are off, the Tr Q3 is conductive, the output terminal O is on an L level and the inversion O becomes an H level. As a result, differential logic is maintained with fewer devices and less operation current.
Inventors:
Blauschild, Robert A.
Linebarger, Daniel J.
Linebarger, Daniel J.
Application Number:
JP13435794A
Publication Date:
May 24, 2004
Filing Date:
June 16, 1994
Export Citation:
Assignee:
PHILIPS ELECTRON NV
International Classes:
H03K19/086; (IPC1-7): H03K19/086
Attorney, Agent or Firm:
杉村 興作 （外４名）
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