Title:
INTEGRATION CIRCUIT
Document Type and Number:
Japanese Patent JP3810862
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an integration circuit with an excellent S/N in which a high speed operation is conducted stably.
SOLUTION: An output of a differential amplifier (A1) 14 is connected to buffer amplifiers (B1)16 and (B2)18, an integration capacitor (C)20 is connected to an output of the buffer amplifier (B1)16 and an input S1 of the differential amplifier 14 and an output of the buffer amplifier 18 is connected to the input S1. For an integration period in response to a reset signal, the buffer amplifier 18 is controlled to be in an OFF state, a current flowing to a resistor 12 is charged in an integration capacitor 20, and for a reset period in response to the reset signal, the buffer amplifier 18 is controlled to be in an ON state, the charge stored in the integration capacitor 20 is discharged from each output terminal of the buffer amplifiers (B1)16 and (B2)18.
Inventors:
Hiroshi Tamayama
Application Number:
JP15194496A
Publication Date:
August 16, 2006
Filing Date:
June 13, 1996
Export Citation:
Assignee:
Fuji Photo Film Co., Ltd.
International Classes:
G06G7/186; H04N5/335; H04N5/357; H04N5/363; (IPC1-7): H04N5/335
Domestic Patent References:
| JP62230268A | ||||
| JP61149473U | ||||
| JP63034798A | ||||
| JP57153378A | ||||
| JP57198647U |
Attorney, Agent or Firm:
Takao Katori
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