PURPOSE: To reduce an error in a high frequency by obtaining an integral output by an output of an adding means for mutually adding each output of a first multiplying means for multiplying a weight coefficient to each output signal, respectively of a delay means.
CONSTITUTION: Between an input terminal 1 to which a digital signal is inputted and an output terminal 2 for outputting an integral value, an adder 3, input delaying circuits D1-D8, weight coefficient multipliers K1-K9, an output delaying circuit 4, and a correction coefficient multiplier 7 are provided. In such a state, delay input signals of plural stages for giving successively a delay of a sampling period or the time being equal to its integer multiple to an input signal having a prescribed period and consisting of an hourly discrete value are obtained. Also, a multiplication output is obtained by multiplying a prescribed weight coefficient to each delay output signal, and an integral output is obtained by adding mutually each multiplication output thereof in the adder 3. In such a way, an error can be corrected by the weight coefficient, and the integral output of high accuracy can be obtained.
| JP2560344 | [Name of device] Small electronic calculator |
| JPS59197936 | DIGITAL SIGNAL PROCESSING SYSTEM |
HOSOYA SHINICHI
AOKI MINORU
IWATSUU AISERU KK