Title:
INTEGRATOR ENABLED WITH OUTPUT COMPENSATION
Document Type and Number:
Japanese Patent JP2948510
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To output the same integration result for the same bit pattern even if the variation of an integrating period, a semiconductor process and power source voltage, etc., exists.
SOLUTION: This integrator is provided with a first integrator 1 having a first amplifier 1 and integrating reference voltage during an integrating period, a second integrator having a second amplifier 11 and integrating an input signal during the integrating period and a control means 7 outputting the signal adjusting the gain of the first amplifier 1 to the first amplifier 1 and adjusting the gain of the second amplifier 11 by using the signal adjusting this gain, so that the output of the first integrator may be changed according to the integrating period.
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Inventors:
TAMURA TETSUYA
TERUKINA ASAO
NOZAWA TOORU
KOYAMA SEIJI
MAATEIN HASUNAA
TERUKINA ASAO
NOZAWA TOORU
KOYAMA SEIJI
MAATEIN HASUNAA
Application Number:
JP21033995A
Publication Date:
September 13, 1999
Filing Date:
August 18, 1995
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G06G7/18; G06G7/184; G11B5/012; G11B5/027; G11B5/09; G11B20/10; H03F3/34; G11B5/035; (IPC1-7): G06G7/18; G11B5/027; G11B5/09; H03F3/34
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)