Title:
積分器リセット機構
Document Type and Number:
Japanese Patent JP2007532011
Kind Code:
A
Abstract:
An integrator with a reset mechanism comprises an integration capacitor and a replacement integration capacitor, wherein the integration capacitor is replaced with the replacement integration capacitor during a reset operation. A method of resetting an integrator comprises temporarily removing an integration capacitor and replacing the integration capacitor with a reset capacitor during a reset operation of the integrator. The method may further comprise temporarily removing the integration capacitor and replacing it with a reset capacitor multiple times during a single reset operation of the integrator.
Inventors:
Delight, Guy
Relivend, Reimi
Relivend, Reimi
Application Number:
JP2006520212A
Publication Date:
November 08, 2007
Filing Date:
July 01, 2004
Export Citation:
Assignee:
ZARLINK SEMICONDUCTOR AB
International Classes:
H03M3/02; G06G7/186; H03M1/06; H03M3/00
Domestic Patent References:
| JP2001042014A | 2001-02-16 | |||
| JPH0295024A | 1990-04-05 |
Foreign References:
| US6061009A | 2000-05-09 | |||
| US6169427B1 | 2001-01-02 | |||
| US6362763B1 | 2002-03-26 | |||
| US5796848A | 1998-08-18 |
Attorney, Agent or Firm:
Akio Miyazaki
Ishibashi Masayuki
Masaaki Ogata
Ishibashi Masayuki
Masaaki Ogata