Title:
JUNCTION METHOD FOR SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JPS54118169
Kind Code:
A
Abstract:
PURPOSE:To join the semiconductor element to the package with minimum occurrence of the void. CONSTITUTION:The lowering of collet 4 is stopped when semiconductor element 1 soft-approaching touches partially solder 3 of package 2. Then the solder is get accustomed to the joint surface of the element, and the element temperature is raised by the heat of the solder. After about 0.2 second, the collet is lowered down again to make the whole joint surface touch the solder. In this case, the lowering speed of the collet is set preferably identical to that of the soft approach. The collet is swung after lowered down to the fixed position, thus completing the junction. With this method, the occurrence of the void can be elminated almost perfectly.
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Inventors:
SHIBATA SHINICHI
Application Number:
JP2574578A
Publication Date:
September 13, 1979
Filing Date:
March 07, 1978
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/52; H01L21/58; (IPC1-7): H01L21/58
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