To provide a layout verification device for correctly setting the voltage of a conductive layer contained in layout data.

A layout verification device comprises a voltage setting part 20 for setting the layout voltage of each of plural conductive layers contained layout data of a semiconductor device, and a verifying part 30 for verifying, based on a design rule, the layout data in which the layout voltage has been set. The voltage setting part 20 comprises a voltage recognizing part 21 for recognizing a first semiconductor layer 72 having a first conductivity type as having GND voltage and recognizing a second semiconductor layer 74 and a third semiconductor layer 73 having a second conductivity type as having a first voltage, with respect to a first element 70 operating at the first voltage contained in the layout data, a GND setting part 22 for setting to the GND voltage, the layout voltages of plural first conductive layers 90, 91, and 92 to which the GND voltage of the first semiconductor layer 72 is propagated and which is connected to the first semiconductor layer 72 and the second semiconductor layer 74, and a power source voltage setting part 23 for setting to the first voltage, the layout voltage of a second conductive layer 93 to which the first voltage of the third semiconductor layer 73 is propagated after the layout voltages of the plural first conductive layers 90, 91, and 92 are set to the GND voltage.