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Title:
LINE EQUALIZING CIRCUIT
Document Type and Number:
Japanese Patent JPH06152340
Kind Code:
A
Abstract:

PURPOSE: To approximately and automatically equalize a received digital signal with respect to its required equalizing band width with a simple constitution in respect of a line equalizing circuit for automatically equalizing the received digital signal in accordance with line length.

CONSTITUTION: The line equalizing circuit is provided with a pulse transformer 1 for inputting a digital signal received from an input terminal 5 to the primary side and outputting the digital signal as a phase-inverted signal from the secondary side, a high pass filter 2 for adding the phaseinverted signal obtained from the secondary side of the pulse transformer 1 to the digital signal and transistors(TRs) 3, 4 for adding a phase-inverted signal obtained by cutting off a low frequency component by the filter 2 to their bases, and constituted so that the emitters of the TRs 3, 4 are mutually connected in common to obtain push-pull connection and equalized digital signals are outputted from output terminals 6 connected to the collectors of the TRs 3, 4.


Inventors:
KUWANA ISAMU
Application Number:
JP29103692A
Publication Date:
May 31, 1994
Filing Date:
October 29, 1992
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03K5/02; H03H15/00; H03H17/00; H03H21/00; H04B3/06; (IPC1-7): H03K5/02; H03H17/00; H04B3/06
Attorney, Agent or Firm:
Shoji Kashiwaya (1 person outside)