PURPOSE: To attain high speed loop data transmission by replacing succeeding data information and data information to be sent into serial data and transmitting them when address coincidence is detected at a point of time when synchronizing information and address information are received.

CONSTITUTION: When a serial signal is received, a carrier signal (b), an address carrier (c), an address comparison timing (e), an output latch timing (g), an output pulse timing (s), and an output gate timing (t) are generated by a synchronizing carrier and timing generation circuit 8. When the address is coincident by a comparator 12, a parallel data (i) subjected to serial/parallel conversion of a data part in a data part serial/parallel converter 16 is latched by an output gate circuit 17. Moreover, the output data (i) is outputted to a data bus for a prescribed time by using a gate signal (k) generated through the gate 19 in the output gate timing (t).