Title:
LOW SUPPLY VOLTAGE ANALOG MULTIPLIER
Document Type and Number:
Japanese Patent JP3548127
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a low supply voltage analog multiplier for supplying an extremely low supply voltage and improving the linearity of input while keeping a sufficient speed by performing the cascade connection of plural stages.
SOLUTION: A pair of differential cells 10 and 11 are provided and the respective differential cells are provided with a pair of bipolar transistors 2, 3, 6 and 7 whose emitters are connected to each other. The first transistors 2 and 6 of the respective cells 10 and 11 receive input signals IN+ and IN- at the base terminals and the collector terminals are connected to a first reference voltage Vcc through bias members 4 and 8. The second transistors 3 and 7 of the respective cells are diode constitution and the cells are mutually connected at a common node A corresponding to the base terminals of the second transistors 3 and 7 of the respective pairs.
Inventors:
Valerio Pisati
Marco Catzaniga
Alessandro Venca
Marco Catzaniga
Alessandro Venca
Application Number:
JP2001052695A
Publication Date:
July 28, 2004
Filing Date:
February 27, 2001
Export Citation:
Assignee:
STMicroelectronics S.r.l.
International Classes:
G06G7/163; H03D7/14; G06G7/16; (IPC1-7): G06G7/16
Domestic Patent References:
| JP8050625A |
Foreign References:
| EP0296131A1 |
Attorney, Agent or Firm:
Michiteru Soga
Michiharu Soga
Yutaka Ikeya
Hidetoshi Furukawa
Suzuki Kenchi
Keiro Mochizuki
Kajinami order
Taizo Shiraishi
Michiharu Soga
Yutaka Ikeya
Hidetoshi Furukawa
Suzuki Kenchi
Keiro Mochizuki
Kajinami order
Taizo Shiraishi
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