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Title:
MANUFACTURE OF MULTILAYER INTERCONNECTION BOARD
Document Type and Number:
Japanese Patent JPH025596
Kind Code:
A
Abstract:

PURPOSE: To prepare a simply designed multilayer interconnection board capable of mounting a high output integrated circuit (IC) by forming not only a multilayer circuit on an aluminum nitride substrate but also a metal conductor on an IC mounting circuit to thereby allow direct mounting of the high output IC.

CONSTITUTION: A conductor layer is formed on the surface of an aluminum nitride sintered body 1. The conductor layer includes a wiring part 2a and a die attaching part 2b. Then, a polyimide film 3 is formed. This polyimide film 3 is formed by subjecting the body to the process steps of: coating a photosensitive polyimide precursor varnish on the surface of the aluminum nitride sintered body 1 including the conductor layer parts 2a, 2b; exposing a predetermined part of the photosensitive polyimide precursor varnish using a glass mask; developing this in a predetermined developing solution to obtain a via hole pattern 4; and then heating the obtained member. By repeating these process steps, a multilayer circuit with as many layers as desired can be formed.


Inventors:
YAMAMOTO HIROAKI
Application Number:
JP15730488A
Publication Date:
January 10, 1990
Filing Date:
June 24, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L23/12; H05K3/46; H05K3/00; (IPC1-7): H01L23/12; H05K3/46
Domestic Patent References:
JPS57208158A1982-12-21
JPS5893296A1983-06-02
JPS59151498A1984-08-29
JPS6337694A1988-02-18
JPS60178688A1985-09-12
JPS60180954A1985-09-14
JPS6257239A1987-03-12
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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