Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS58132949
Kind Code:
A
Abstract:
PURPOSE:To accomplish the flattening of the surface of an electrically insulated layer located between wiring patterns by a method wherein an etching which is partially different in thickness is performed on a passivation layer using an ion implantation. CONSTITUTION:After an SiO2 layer 11', which is a passivation layer, is coated on the stepping face generated by providing a wiring layer 12 on an SiO2 layer 11 of passivated one located on the substrate, a high molecule material layer 13 of low viscosity, the barrier property of ion implantation which is in proportion to the layer thickness, is applied in a fluidized state, an ion implantation is performed, and then an ethcing having partially different thickness is performed on the layer 11. As a result, the depth from the surface which was formed by application of the high molecule material becomes equaled to the layer 11' thickness plus ion implantation thickness, the surface of the high molecule material of low viscosity is considered to be perfectly plane, and an excellent flatness of the bottom face of the ion-implanted layer can be obtained.
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Inventors:
FURUGUCHI SHIGEO
KINOSHITA HIROSHI
KATOU CHIHARU
KUMAMARU KUNIAKI
KINOSHITA HIROSHI
KATOU CHIHARU
KUMAMARU KUNIAKI
Application Number:
JP1431182A
Publication Date:
August 08, 1983
Filing Date:
February 02, 1982
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/3213; H01L21/302; H01L21/3065; H01L21/311; (IPC1-7): H01L21/302; H01L21/88
Attorney, Agent or Firm:
Norio Ogo (1 outside)